Characterization of FDSOI Technology for Energy-Efficient Cryo-CMOS Circuits

High-performance cryo-CMOS circuits are the foundation for quantum computing hardware. The energy efficiency of cryo-CMOS circuits is limited by the changing operating point of the device as the temperature drops. Operating point calibration becomes imperative to achieve energy-efficient designs, yet accurate threshold-voltage calibration at deep-cryogenic temperatures proves challenging. At cryogenic temperatures, conventional threshold-voltage extraction methods fail as the device operating point exhibits a nonlinear shift with temperature, rendering standard threshold voltage extraction methods unreliable, particularly in the low-V GS regime where cryo-CMOS circuits are typically biased for energy efficiency. This work characterizes flip-well 22 nm fully-depleted silicon-on-insulator (FDSOI) technology and demonstrates a robust methodology for operating point calibration using back-gate control. Established extraction methods, including constant current, maximum transconductance, second-derivative, third-derivative, linear extraction, and transconductance-to-current ratio, are performed to assess their applicability under cryogenic conditions. In doing so, we demonstrate that back-gate tuning provides an effective and scalable mechanism for compensating operating-point shifts without emphasis on the absolute value of the threshold voltage. Calibrated threshold voltage results across temperature are presented for a 22 nm FDSOI super-low-V T (SLVT) transistor using body bias sweeps from 0 to +2 V. To enable circuitlevel calibration in the low-V GS regime, this work identifies the body-coefficient η as a relevant metric for biasing, capturing the effective sensitivity of gate threshold voltage to back-gate bias. The extracted η exhibits nonlinearity with respect to both temperature and bias conditions, providing a physically meaningful and design-relevant parameter for energy-efficient cryo-CMOS calibration.