In-Memory Vector Operations Using Commercial Off-the-Shelf 6T SRAM

In-memory computing promises significant advancements in efficiency, but achieving seamless integration with highly optimized commercial SRAM cells remains profoundly challenging. While numerous state-of-the-art techniques propose new solutions, they often require modifications to the core SRAM bitcell, sacrificing the essential advantages in area, power, and reliability that mature industry-standard SRAM designs provide. Our approach introduces a suite of novel sense amplifiers (SAs) tailored for commercial 6T SRAM-based memory arrays. These sense amplifiers enable efficient execution of fundamental logic operations (AND, OR, XOR) directly within the SRAM array while maintaining its standard read/write functionality. Our proposed SA designs are optimized to operate within the tight constraints of foundry-provided (i.e., off-the-shelf commercial) 22nm 6T SRAMs, ensuring seamless integration with existing memory arrays while delivering reliable vector logic-in-memory computing capabilities. Compared to prior work, our SA designs achieve a 2-2.41× reduction in area for NAND and OR operations, and a 3× reduction for XOR. Additionally, dynamic power consumption is reduced by 1.2-4×, and error rates are suppressed by up to 19×, as demonstrated through Monte-Carlo and post-layout simulations. Robustness was further evaluated under varying temperature and voltage conditions, demonstrating thermal resilience across most proposed designs and reliable operation with up to a 0.1 V reduction over the nominal supply voltage.