An ADC-Direct Neural Recording Architecture With Always-Nyquist Lossless Adaptive Resolution and Memory-Assisted PI Feedback

This paper presents an ADC-direct neural recording front-end with event-preserving adaptive-resolution compression that targets high-channel-count implantable BCIs where wireless throughput dominates the power budget. Resolution is adapted by switching the modulator oversampling ratio (OSR) and updating the decimator by the same factor, maintaining an always-Nyquist output data rate while changing the effective sample size rather than sampling instants or quantizer structure. The mixed-signal core employs a differential-difference transconductance input stage that applies feedback subtraction without loading the electrode node, enabling DC coupling and input chopping for flicker-noise suppression while preserving high input impedance. Second-order noise shaping is realized using a proportionalintegral (PI) loop implemented with a memory-assisted variablestep feedback DAC, avoiding high-resolution multi-bit DACs and associated area/linearity overhead. Fabricated in 130-nm CMOS, the front-end achieves 161 nV/ √ Hz input-referred noise density (4.8 µVrms integrated), 58.7 dB SNDR, and tolerates up to 350 mV differential offset while maintaining >53 dB SNR. With a 10/4-bit adaptive-resolution setting, the proposed compression reduces the transmitter power share from 95% to 46%, creating margin for increased channel count and/or more capable on-chip processing within a fixed implant power budget.