Temperature-Dependent Soft-Error Analysis from 300 K to 77 K in Nanosheet and CFET

We investigate the impact of cryogenic temperatures on the Single Event Upset (SEU) reliability of the Gate-All-Around (GAA) Nanosheet FET (NSFET) and Complementary FET (CFET) devices. At the device level, we assess heavy-ion radiation (HIR)-induced transients and carrier profiles and compare CFET and NSFET for temperatures from 300 K to 77 K. For low doses, the peak current for both CFET and NSFET increases sharply as the temperature decreases into the cryogenic regime. However, for high doses, the peak current decreases with the temperature. Further, collection time increases with incident dose and temperature due to an increase in electron-hole pair (EHP) generation and a decrease in carrier mobility. CFET in comparison to NSFET, shows 32% higher peak current and requires 14.3% more time for charge collection at 300 K and 1 MeVcm 2 mg-1. At 77 K the difference is 23.7% and 13.8%, respectively. The circuit-level radiation resilience of CFET and NSFET-based CMOS inverters and 6T-Static Random Access Memories (SRAMs) also improves at cryogenic temperatures. We report that the SEU reliability of CFETbased CMOS inverters and SRAMs is better than the NSFETbased circuits for all doses and temperatures. Next, the impact of temperature on HIR-induced voltage drop, failure time, and critical LET for inverter and SRAM circuits is studied and compared for the two devices. For temperature in the range from 300 K to 77 K, the inverter voltage drop, failure time (for LET=1 MeVcm 2 mg-1), and critical LET with CFET are, on average, 36%, 3.6%, and 10% improved in comparison to NSFET, respectively. Similarly, with CFET, the improvements in SRAM storage node voltage drop and the critical LET are 2.4% and 20%, respectively.