Reliability-aware scaling of nanoscale transistors: Self-heating and BTI/HCD degradation

As semiconductor devices scale into the sub-5 nm regime, gate-all-around (GAA) nanosheet field-effect transistors (FETs) have emerged as the leading successors to FinFETs, offering superior electrostatic control and scalability. However, reliability challenges; including self-heating effects (SHEs), bias temperature instability (BTI), and hot-carrier degradation (HCD) increasingly threaten device longevity and circuit stability. This review provides a critical synthesis of recent advances in understanding these degradation mechanisms, highlighting their physical origins, stress dependencies, and scaling-induced variability. Beyond summarizing established models, we compare experimental and simulation studies to identify inconsistencies, unresolved questions, and emerging trends. Special attention is given to nanosheet-specific phenomena such as thermal hotspots, corner-induced field amplification, and stochastic trap dynamics, which exacerbate reliability risks compared to FinFETs. We further outline design-technology co-optimization (DTCO) strategies, including adaptive biasing, advanced thermal management, and reliability-aware circuit modeling. Finally, we propose future research directions spanning CFET integration, multi-physics-based reliability prediction, and novel materials for thermal dissipation. By consolidating current knowledge and projecting open challenges, this article aims to guide both academic and industrial efforts toward ensuring robust, long-term functionality of nanosheet and complementary FET technologies in next-generation nodes.