Estimating Retention Time in 3D TLC NAND Flash
Abstract
Retention time of flash memory is an important metric utilized in various flash controller mechanisms (e.g., error modeling and configuring read voltage level). By losing track of retention time during the OFF phase, the flash controller loses track of the flash cell state. This knowledge gap during the OFF state results in higher Raw Bit Error Rates (RBER) in flash during consecutive reads, as suboptimal read voltages are being used. Leakage weakens stored charges in the flash cells, but - without retention time - the flash controller cannot anticipate the leakage and thus cannot select the matching read voltages for the weakened cells. This work aims to close the knowledge gap and estimate “equivalent retention time” after power ON. A specific memory block is prepared, and during each consecutive power-ON event, this reference block is read, and its data is used in a lightweight machine learning approach to determine the retention time that has passed. This enables various existing techniques to improve the flash memory state and allows the flash controller to select the correct read settings based on the current charge degradation in the flash cells. We present the first work, which provides such a retention time model with the following contributions: a) We solely utilize measurement data, which is already obtained during manufacturing, burn-in, or operation. b) Our Machine Learning (ML) model is lightweight enough to be deployed on the limited processing power of flash controllers. c) Our model can deal with the considerable chip-tochip, block-to-block, and page-to-page variation in current flash memory modules. d) We calibrate and validate our approach with commercial-off-the-shelf (COTS) BiCS5 flash memory obtained with a COTS flash controller with a special firmware to extract and monitor read and writes in BiCS5 flash. Overall, our retention time approach enables existing flash recovery and flash read methods to accurately estimate the current flash state, thereby reducing flash error rates. This is made possible because our approach can predict retention times with an accuracy of 98.2% and a deviation of just 1.42% in our reference block, despite the high variations in flash technology.
Fields of Study & Subjects
Advanced Data Storage Technologies
Semiconductor materials and devices
Low-power high-performance VLSI design
Publication details
- Publication date
- 16 January 2026
- Document type
- Preprint