Fully Automated Schematic and Layout Synthesis of Broadband LC Matching Networks with Arbitrary Topologies for RFIC Designs

Broadband impedance matching is a cornerstone of radio frequency integrated circuit design. While LC matching networks are widely used, their implementation is often hindered by restricted design spaces, labor-intensive manual tuning, and high computational costs. This paper presents a fully automated framework for the synthesis and layout generation of arbitrary LC matching networks, addressing the inefficiencies of traditional workflows. The proposed framework integrates topology-agnostic network synthesis via the combinatorial optimization of formally encoded LC units. To eliminate manual layout drafting, an automated placement and routing engine is employed, followed by a layout sizing optimization process to bridge the performance gap between schematic and layout. Furthermore, to accelerate the electromagnetic-aware refinement, the framework utilizes variational auto-encoders to compress high-dimensional S-parameter data into low-dimensional latent representations, enabling highly efficient Bayesian optimization. The methodology is validated through the implementation of a K/Ka-band lownoise amplifier and a Ku-band single-pole double-throw switch in a 40-nm CMOS process. Post-layout simulation results demonstrate that this framework drastically reduces design cycle time and complexity while maintaining competitive high-frequency performance compared to conventional manual design flows.