LLM-Aided Verification Gap Detection: A Methodology for Identifying Missing Checkers in UVM Testbenches
Abstract
High code coverage does not guarantee complete verification. Coverage metrics measure where tests exercise the design, but not whether outputs are actually checked. This gap between exercising code and validating results-the verification gap-allows bugs to escape even with 99%+ coverage. When outputs differ between correct and faulty RTL, but all tests still pass, checkers are missing. This paper presents a novel methodology for identifying verification gaps through LLM-aided analysis of mutation-induced behavioral divergence. The approach combines automated fault injection with structured LLM prompting to systematically detect missing checkers that coverage metrics cannot reveal. The theoretical foundation rests upon a constructive proof: injection of semantically non-equivalent mutations into golden RTL, followed by differential simulation, exposes precisely those output behaviors that evade checker scrutiny. The workflow is straightforward: (i) introduce a small change (mutation) to the RTL, (ii) run the same tests on both original and mutated versions, (iii) if outputs differ but tests pass, a gap exists, (iv) use an LLM to suggest the missing checker, and (v) validate the fix. The entire detection cycle takes about 80 seconds per mutation. Proof-of-concept validation on two representative IP blocks-a round-robin arbiter (350 LOC, algorithmic complexity) and synchronous FIFO (150 LOC, numeric boundaries)-demonstrates methodology feasibility: 4× time reduction, 100% precision (zero false positives), and cross-domain applicability across distinct fault morphologies. Break-even analysis yields N * ≈ 10 faults for initial deployment with asymptotic reduction to N * ≈ 2 upon amortization. The results establish feasibility of LLM-aided gap detection as a complement to traditional coverage-driven verification.
Fields of Study & Subjects
Software Testing and Debugging Techniques
VLSI and Analog Circuit Testing
Embedded Systems Design Techniques
Publication details
- Publication date
- 10 February 2026
- Language
- EN
- Document type
- Preprint