HiSNN: A Hardware-Informed Spiking Neural Network Simulator with Accurate and Efficient Power-Performance-Area Evaluations

This work reports HiSNN, a hardware-informed SNN simulator by incorporating the circuit module information for accurate merit evaluations of the power-performance-area. Characteristics of the synapses and neurons, including plasticity regulation, event-related power, and trace, etc., are abstracted into a proposed neuromorphic component library (NCL). The characteristics are obtained from SPICE simulations of circuit implementations of the SNN components. By calling the NCL, which combines tables, surrogate models, and parameterization, HiSNN traces the spiking events, calculates the membrane potential, makes the spiking decision, monitors the power in the time domain, and eventually outputs the performance, power, and area (PPA). By this hierarchy, accurate evaluations of SNN functions are obtained with higher efficiency. Benchmarks are performed with SPICE simulations on different tasks. For MNIST handwritten digit recognition and abnormal ECG detection, the error rate of HiSNN does not exceed 3%, and the energy consumption error does not exceed 5%. HiSNN achieves about 300× speedup in the learning phase, and about 3000× speedup in the inference phase. When the network scale increases, HiSNN has a better completion rate for tasks, and its efficiency advantage becomes more significant. HiSNN serves as a fast simulator for algorithm technology co-optimizations of the SNN hardware designs with wide technology coverage.