Studies on seam free gap fill process for STI based on 28 nm CMOS technology

This study addresses the filling challenges associated with high aspect ratio, non-standard V-shaped shallow trench isolation (STI) structures in 28 nm complementary metal-oxide-semiconductor (CMOS) technology. Such structures are prone to forming center seams after deposition, compromising device isolation reliability. A combined approach employing high aspect ratio process (HARP) deposition and post-steam high-temperature annealing was adopted to achieve seam free filling. Through cross-experimentation, the effects of a novel HARP deposition process and an innovative high-temperature annealing technique on the shrinkage rate of silicon oxide films and the seam morphology within trenches were systematically investigated. The results revealed that optimizing either process alone could not completely eliminate micro-seams at the bottom of the V-shaped structure. The ultimate solution emphasizes process synergy: integrating the novel HARP deposition with pulsed high-temperature annealing while introducing hydrogen chloride (HCl) as an auxiliary gas during the annealing step. This combined mechanism enables precise control over film densification and utilizes the vapor-phase etching effect of HCl to effectively remove weak interfacial regions, thereby achieving high-quality, seam free filling in high aspect ratio, non-standard V-shaped STI structures. This research provides an effective process route for integrating complex three-dimensional structures at advanced technology nodes.