Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Silicon carbide (SiC) has emerged as a leading material for high-power applications. However, the high density of interface states (D it ) at the SiO 2 /SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4H-SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based D it extraction algorithm. The results demonstrate that NO PDA effectively reduces D it not only near the conduction band edge but also towards the valence band, yielding improved channel mobility (µ FE ) and enhanced threshold voltage stability.