Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

The pursuit of ever-higher system efficiency and power density in power electronic applications paves the way for an increased utilization of wide bandgap semiconductor devices such as silicon carbide (SiC) MOSFETs, due to reduced conduction and switching losses compared to silicon. For real-world application reliable operation along its lifetime is of utmost importance. To assure robust operation in electric drives and traction inverters SiC MOSFETs are switched bipolar to prevent parasitic turn on. Recently, it has been shown that not only bias temperature instability, but also gate-switching instability in bipolar switched applications has to be considered as a reliability concern for SiC MOSFET. While in gate switching stress tests usually only critically damped conditions are investigated irrespective of rise and fall times, in real-world applications gate voltage overshoots may occur and a broad variety of slew rates may be used depending on the individual power converter design. Therefore, this work investigates the influence of gate voltage overshoot and voltage slopes on threshold voltage aging using high frequencies and online degradation monitoring. It is shown that overshoots have a dominating impact on the overall degradation, while the gate voltage slope impacts minorly.