Optimization of Redistributed Layers between Heterogeneous Devices for Wafer-Level Integration

Pseudo-SOC (System on Chip) technology is integration technology consisting of the chips embedded in epoxy resin and redistributed (thin-film metal) layer formed with semiconductor process, realizing the complementary advantages of SOC and SIP (System in Package) technology. In this technology, high-density integration is achieved by integrating heterogeneous chips with very narrow gap in the resin and without interposer substrate. In this paper, the authors focused on the improvement in the pitch of the redistributed layer by improving the planarization and the adhesivity of the underlying layer. By improving the transfer process of the chips and the printing process of the resin, the resin was formed between the chips set with narrow gap of 100μm with good filling ratio. Furthermore, by controlling the formation condition of the planar layer, redistributed layer with a fine pitch of 15μm/15μm in line and space was achieved. Thus, the redistributed layer with a pitch 3 times finer than that of the device previously developed was realized, leading to the miniaturization of pseudo-SOC.