Design & Analysis of 5 nm PDSOI and FDSOI n-MOSFETs for Ultra-Low Power Applications with High-k Dielectric Materials

In this study, a comparison of 5 nm PDSOI and FDSOI n-MOSFETs with SiO2 and high-k gate dielectrics is carried out using Silvaco TCAD ATLAS platform with necessary models. SOI architectures (PDSOI/FDSOI) offer enhanced electrostatic control compared to bulk CMOS, which suffers from threshold instability, SCEs and leakage near the 20 nm node. In this scaling, various high-k dielectric materials were explored for gate oxide. Among those, Ta2O5 shows comparatively much better results with respect to the optimized SiO2-gated device of the same SOI architecture. The PDSOI device showed 39.15% lower Threshold Voltage (Vth), 26.5% improved Subthreshold-Swing (SS), leakage current (IOFF) of 2.17 × 10−10 A, and ION/IOFF ratio of 1.64 × 106, making it suitable for analog and near-threshold logic applications. The FDSOI device exhibited closely unchanged Vth of 0.6604 V, 34% improved SS, ultra-low IOFF of 1.69 × 10−13 A and ION/IOFF ratio 7.41 × 109 favoring use in high-speed and ultra-low-leakage digital systems. This paper gives valuable insight and guidelines for selecting optimal SOI architectures and gate dielectric materials in future ultra-scaled, energy-efficient, and high-performance integrated circuits.