NeonCROSS: Vectorized Implementation of Post-Quantum Signature CROSS on Cortex-A72 and Apple M3

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Authors: Hanyu Wei, W. D. Li, Yunlei Zhao
Cited by: 0

Abstract

The advancement of quantum computing threatens traditional public-key cryptographic systems, prompting the development of post-quantum cryptography (PQC). As part of the NIST PQC standardization process, code-based cryptographic schemes have gained attention due to their strong security foundations and longstanding resistance to both classical and quantum attacks. CROSS is a code-based digital signature scheme that relies on the hardness of decoding restricted vectors. It is designed to offer a flexible trade-off between signature size and speed performance, making it a promising candidate for post-quantum cryptography. This work introduces a faster modular reduction method for the pseudo-Mersenne prime in CROSS, significantly improving modular arithmetic efficiency. The proposed method is also applicable to other primes of similar structure. In addition, we present vectorized implementations of key operations. Matrix-vector multiplication is vectorized with parameter-specific strategies, and the processing of tree structures in CROSS is optimized using batch hashing methods adapted to the Neon extension. This paper presents the first vectorized implementation of the CROSS digital signature scheme on the ARMv8-A architecture, leveraging the Neon extension for optimized performance. The implementation is evaluated on both ARM Cortex-A72 and Apple M3 processors, achieving up to 63.3% speedup in signature generation and 56.3% in verification, demonstrating significant performance improvements over the reference implementation. These results highlight the potential of CROSS for efficient post-quantum cryptography on ARMv8-A architecture.

Fields of Study & Subjects

Cryptography and Residue Arithmetic Cryptographic Implementations and Security Cryptography and Data Security

Publication details

Journal / source
IACR Transactions on Cryptographic Hardware and Embedded Systems
Volume
2026
Issue
1
Pages
250–272
Publication date
16 January 2026