A Mirrored-Circuits Approach for Low-Latency and Low-Randomness Composable PINI Gadgets

Masking is a crucial countermeasure against side-channel attacks, yet it is challenging to implement in hardware. At CHES 2024, Kumar S.V. et al. introduced the concept of Time Sharing Masking (TSM) for constructing low-latency first-order PINI gadgets. While TSM has demonstrated its effectiveness, we propose a new approach called mirrored-circuits to further enhance hardware performance. This approach constructs two MIRROR circuits that share randomness between them. For Boolean functions represented in the Algebraic Normal Form (ANF), the mirroredcircuits approach outperforms previous works in terms of the number of randomness bits and registers. By reconstructing the ANF form, the above two metrics can be further optimized using an SMT approach. We provide experimental results from several case studies to evaluate the efficiency of our approach. For 4-bit S-boxes, we achieve substantial reductions in randomness, delay, and area. Specifically, the 1-cycle SKINNY S-box achieves reductions of 50%, 37%, and 29% in randomness, delay, and area, respectively. For the AES S-box, the 1-cycle design minimizes randomness by 49%, and the 2-cycle design reduces randomness by 35% and area by 47%. To ensure the security of our schemes, we conduct comprehensive verification through three dimensions: theoretical proof, formal verification using SILVER, and FPGA-based experiments.