YATA: Yet Another TFHE Accelerator with Key Compression and Radix-8 NTT

This paper introduces a silicon-proven ASIC accelerator, YATA, specifically designed for TFHE’s most demanding operation, the BlindRotate. The architecture tackles the main bottleneck in TFHE—massive memory bandwidth—by applying Key Compression to reduce the size of the bootstrapping key significantly. It further enhances performance and area efficiency through a novel Radix-8 Number Theoretic Transform (NTT), using carefully chosen prime moduli that allow cost-effective constant multiplications and streamlined modular reductions. Fabricated in a 22nm process, YATA’s design occupies only 5.93mm2 and achieves 0.32 ms BlindRotate latency for the targeted security parameters. YATA offers a practical route toward fully homomorphic encryption deployments on customized hardware. Overall, this work demonstrates the feasibility of ASIC-based accelerators for TFHE in latency and power efficiency, establishing a foundation for future TFHE-based privacy-preserving applications.