WiP: Flush-based Cache Attacks on Modern / Multi-Socket x86 systems

Flush-based cache attacks have been extensively studied and leveraged, yet their behavior on today's complex x86 platforms is not fully understood. Notably, as cache and memory latency depend on the physical layout of cores, caches, and NUMA nodes, system topology increasingly influences the latencies underlying such attacks. We thus investigate the impact of this growing complexity on the effectiveness of flush-based attacks. We present a large-scale, topology-aware study of Flush+Reload and Flush+Flush across 36 Intel and AMD, single- and multi-socket systems, with server and client CPUs. We show topology-induced contributions dominate the latency variations. In particular, NUMA contribution on multi-socket systems makes topology-unaware attacks unreliable. Our topology-aware calibration accounts for topological parameters like attacker/victim cores, memory NUMA node, and target address, improving error rates and attack viability. We demonstrate Flush+Flush works on AMD targets, and is often more accurate than Flush+Reload on modern x86 platforms. Finally, we introduce Load/Flush+Reload, a covert-channel comparing invalid to shared loads, with double the true capacity than Flush+Reload/Flush+Flush. Our results show that topology awareness is required for dependable cache attacks on recent platforms, and provide practical guidance for attackers and defenders.