Voltage-controlled Oscillators in Phase-locked Loops: Recent Advances and Design Considerations

Voltage-Controlled Oscillators (VCOs) constitute a fundamental component in Phase-Locked Loops (PLLs), exerting direct influence on frequency precision, phase noise, power dissipation, and overall system resilience. In the context of the rapid advancement of wireless communication standards, high-speed serial links, and low-power System-on-Chip (SoC) designs, Voltage-Controlled Oscillators (VCOs) have experienced substantial improvements in recent years. VCOs are essential components in PLLs, which are pivotal in diverse applications, including wireless communications, clock generation, and data recovery systems. This paper delves into the latest developments in VCO design, highlighting innovations that improve phase noise, tuning range, linearity, power efficiency, and integration in modern CMOS technologies. Various VCO architectures, such as ring, LC-tank, and hybrid designs, are reviewed with an emphasis on their suitability for low-power and high-frequency applications. Furthermore, key design trade-offs and considerations, including noise sources, frequency stability, and layout techniques, are discussed in the context of PLL system-level requirements. The survey further examines emerging VCO design paradigms, including Digitally Controlled Oscillators (DCOs), adaptive calibration techniques, and machine learning-assisted optimization methodologies. This survey aims to guide designers toward selecting and implementing VCOs that meet stringent performance metrics in next-generation PLL-based systems.