A High-Speed Differential Hybrid Voltage Level Shifter With Simultaneous Multi-Level Outputs

This paper presents a low-jitter hybrid voltage level shifter (HVLS) architecture for high-speed mixed-signal and digital power-amplifier applications. The proposed design employs a regenerative cross-coupled feedback network to simultaneously generate two synchronized voltage-domain outputs (e.g., the nominal supply voltage VDDL and one at twice its value, VDDH = 2VDDL). This enables direct drive of cascoded class-D power amplifiers without additional delay-calibration circuitry, amongst other mixed-signal applications. A prototype HVLS circuit, together with an impedance-matching network and a pre-driver for high-speed off-chip characterization, was fabricated in a 22-nm FD-SOI process technology. The total die area, including all interface circuitry, is 477 x 462 um^2, while the active area of the HVLS core is 3.26 x 2 um^2. Measured at 12.2 GHz, the circuit dissipates 427.8 uW and achieves a measured rms jitter below 43 fs (10 Hz-500 kHz), limited by the noise floor of the measurement setup.