Veryl Hardware Description Language

What's Changed Breaking Changes 🛠 Add non-portable construct opt-in and dependency policy by @dalance in https://github.com/veryl-lang/veryl/pull/3268 New Features 🎉 feat(analyzer): infer generic function arguments from module ports by @AkiyukiOkayasu in https://github.com/veryl-lang/veryl/pull/3197 Replace combinational-loop analysis with sparse SSA by @tignear in https://github.com/veryl-lang/veryl/pull/3161 feat(analyzer): allow importing component namespaces (package, module, interface) by @AkiyukiOkayasu in https://github.com/veryl-lang/veryl/pull/3198 Other Changes fix(analyzer): detect duplicate enum variants with identical x/z values by @dalance in https://github.com/veryl-lang/veryl/pull/3136 Fix hoisted statement-block declarations dropping ifdef guards by @dalance in https://github.com/veryl-lang/veryl/pull/3137 Fix struct/union member separator emitted outside its ifdef guard by @dalance in https://github.com/veryl-lang/veryl/pull/3138 Fix ifdef attribute state leaking across scopes accepting orphan else/elsif by @dalance in https://github.com/veryl-lang/veryl/pull/3139 fix(analyzer): size assignment RHS against the LHS bit-select width by @dalance in https://github.com/veryl-lang/veryl/pull/3145 fix(simulator): stop emitting acc 128-bit dynamic selects and field stores by @dalance in https://github.com/veryl-lang/veryl/pull/3148 Fix emittion of packed array typed with gen const by @taichi-ishitani in https://github.com/veryl-lang/veryl/pull/3142 fix(simulator): AOT-C 128-bit ternary coverage and wide-ternary sign extension by @dalance in https://github.com/veryl-lang/veryl/pull/3149 fix(simulator): AOT cache publish survives process exit by @dalance in https://github.com/veryl-lang/veryl/pull/3150 fix(simulator): one compiler per AOT-C artifact via a cache lock file by @dalance in https://github.com/veryl-lang/veryl/pull/3151 fix(simulator): the compile script lost -O3 to its missing lock argument by @dalance in https://github.com/veryl-lang/veryl/pull/3152 fix(simulator): send the AOT compile's output to a file, not to a closed pipe by @dalance in https://github.com/veryl-lang/veryl/pull/3153 feat(simulator): report the engine a run actually used as degraded_modules by @dalance in https://github.com/veryl-lang/veryl/pull/3154 fix(simulator): reject read-before-write localization by @dalance in https://github.com/veryl-lang/veryl/pull/3155 perf(simulator): elide provably-redundant masks by @dalance in https://github.com/veryl-lang/veryl/pull/3156 fix(simulator): waveform dumping turns comb localization off by @dalance in https://github.com/veryl-lang/veryl/pull/3157 fix(simulator): avoid zero-length wide scratch arrays in AOT-C emit by @dalance in https://github.com/veryl-lang/veryl/pull/3158 Add behavioral tests for combinational-loop analysis by @tignear in https://github.com/veryl-lang/veryl/pull/3159 feat(simulator): change-driven incremental comb settle, on by default by @dalance in https://github.com/veryl-lang/veryl/pull/3160 fix(simulator): AOT-C coverage for a narrow rhs_select field of a wide RHS by @dalance in https://github.com/veryl-lang/veryl/pull/3166 fix(simulator): store a localized wide-RHS def to its C local by @dalance in https://github.com/veryl-lang/veryl/pull/3167 perf(simulator): narrow bit-field stores to their sub-word and merge a window's stores into one register build by @dalance in https://github.com/veryl-lang/veryl/pull/3168 perf(simulator): sink a single-reader comb def to its reader by @dalance in https://github.com/veryl-lang/veryl/pull/3170 perf(simulator): in-place settle-order comb relayout by @dalance in https://github.com/veryl-lang/veryl/pull/3171 perf(simulator): inline single-reader comb defs into their readers by @dalance in https://github.com/veryl-lang/veryl/pull/3172 perf(simulator): coalesce full-coverage field stores into one concat assignment by @dalance in https://github.com/veryl-lang/veryl/pull/3173 perf(simulator): duplicate cheap multi-reader defs (opt-in) and collapse common RHS shapes by @dalance in https://github.com/veryl-lang/veryl/pull/3174 perf(simulator): assemble wide concats, select-RMW stores, and bit broadcasts directly into their destinations by @dalance in https://github.com/veryl-lang/veryl/pull/3175 diag(simulator): fusion veto-shape breakdown and field-store census by @dalance in https://github.com/veryl-lang/veryl/pull/3177 Issue#3130 forloop overflow by @ranaumarnadeem in https://github.com/veryl-lang/veryl/pull/3140 perf(simulator): weight the AOT-C chunk budget by approximate code size by @dalance in https://github.com/veryl-lang/veryl/pull/3179 perf(simulator): pick SLP vectorization per comb source by static wide-op density by @dalance in https://github.com/veryl-lang/veryl/pull/3180 perf(simulator): run the constant-input cone once per instance instead of every settle by @dalance in https://github.com/veryl-lang/veryl/pull/3182 perf(simulator): turn cheap multi-reader duplication on by default by @dalance in https://github.com/veryl-lang/veryl/pull/3183 perf(simulator): merge same-variable bit tests into masked compares and parities by @dalance in https://github.com/veryl-lang/veryl/pull/3184 fix(simulator): give IR-walking threads an explicit stack so deep designs survive debug builds by @dalance in https://github.com/veryl-lang/veryl/pull/3188 perf(simulator): drop dead machinery and retune the incremental sweep by @dalance in https://github.com/veryl-lang/veryl/pull/3189 feat(simulator): decide the incremental settle from a probed activity verdict by @dalance in https://github.com/veryl-lang/veryl/pull/3190 fix(simulator): bound one statement's emitted C and the compiler's address space by @dalance in https://github.com/veryl-lang/veryl/pull/3192 fix(simulator): sweep AOT-C temp artifacts left by compiles that never published by @dalance in https://github.com/veryl-lang/veryl/pull/3193 fix doc HTML escaping by @Kenta11 in https://github.com/veryl-lang/veryl/pull/3178 fix(simulator): bound the version-split fold by expression size by @dalance in https://github.com/veryl-lang/veryl/pull/3194 fix(doc): escape doc comments rendered into HTML table cells by @dalance in https://github.com/veryl-lang/veryl/pull/3195 perf(simulator): run the version split unconditionally by @dalance in https://github.com/veryl-lang/veryl/pull/3196 fix(synthesizer): read a packed multi-dimensional array element at its full width by @dalance in https://github.com/veryl-lang/veryl/pull/3200 fix(synthesizer): write every element of a whole-array assignment destination by @dalance in https://github.com/veryl-lang/veryl/pull/3201 fix(synthesizer): stop double-counting the member offset on a struct member write by @dalance in https://github.com/veryl-lang/veryl/pull/3202 fix(simulator): build a dynamic bit-select for a runtime-indexed hierarchical read by @dalance in https://github.com/veryl-lang/veryl/pull/3203 fix(simulator): support a whole-array assignment from an array-returning function by @dalance in https://github.com/veryl-lang/veryl/pull/3204 fix(synthesizer): synthesize struct and array literals instead of rejecting them by @dalance in https://github.com/veryl-lang/veryl/pull/3205 perf(simulator): enable comb fusion and the comb relayout by default by @dalance in https://github.com/veryl-lang/veryl/pull/3209 fix(analyzer): keep a register when always_ff writes an element more than once by @dalance in https://github.com/veryl-lang/veryl/pull/3210 fix(simulator): support a const array as an array-valued operand by @dalance in https://github.com/veryl-lang/veryl/pull/3211 fix(analyzer): reject a type used as a width or array size by @ranaumarnadeem in https://github.com/veryl-lang/veryl/pull/3206 Fix#3199 by @ranaumarnadeem in https://github.com/veryl-lang/veryl/pull/3207 fix(simulator): expand a sub-array assignment on either side of the index by @dalance in https://github.com/veryl-lang/veryl/pull/3212 fix(simulator): report a dynamic index that leaves a sub-array instead of asserting by @dalance in https://github.com/veryl-lang/veryl/pull/3213 feat(analyzer): resolve a struct member through a hierarchical reference by @dalance in https://github.com/veryl-lang/veryl/pull/3214 fix(simulator): fit a struct constructor member literal to the member width by @dalance in https://github.com/veryl-lang/veryl/pull/3215 feat(analyzer): reject a union constructor by @dalance in https://github.com/veryl-lang/veryl/pull/3216 fix(analyzer): keep the register only when a self-reference reads bits the block already wrote by @dalance in https://github.com/veryl-lang/veryl/pull/3217 perf(simulator): recover word-wide work from per-bit logic and bound the version-split fold by @dalance in https://github.com/veryl-lang/veryl/pull/3218 refactor(simulator): retire the incremental settle by @dalance in https://github.com/veryl-lang/veryl/pull/3219 fix(analyzer): let every cached fragment define the $sv members it uses by @dalance in https://github.com/veryl-lang/veryl/pull/3221 perf(simulator): fuse bit-disjoint writers in the version split by @dalance in https://github.com/veryl-lang/veryl/pull/3222 refactor(simulator): stream a $readmemh image and share its destination list by @dalance in https://github.com/veryl-lang/veryl/pull/3224 feat(simulator): honor $readmemh address directives by @dalance in https://github.com/veryl-lang/veryl/pull/3225 fix(analyzer): connect an unpacked array slice to an instance port element-wise by @dalance in https://github.com/veryl-lang/veryl/pull/3226 fix(simulator): report an unevaluatable