Hardware-in-the-Loop (HIL) Simulation of a Sobel Edge Detection Algorithm for Real-Time Image Processing

This paper presents a comprehensive Hardware-in-the-Loop (HIL) simulation framework for developing and verifying a real-time Sobel edge detection system. Modern image processing applications, such as surveillance and autonomous vehicles, require high-speed edge detection capable of processing video streams in real time. Traditional software implementations often fail to meet strict timing constraints. To address this, we propose a simulation-based design methodology using MATLAB and Simulink to model hardware behavior and verify performance without the immediate need for physical hardware. The study implements an optimized Sobel algorithm using an absolute sum approximation method, which replaces computationally expensive square root operations. We developed a Simulink model with a pipelined architecture to mimic hardware parallelism. The system was validated through HIL simulation, processing video streams with an average processing time of 39.95 milliseconds per frame, achieving a frame rate of 25.03 frames per second. The optimized algorithm achieved a speedup factor of up to 1.46 compared to the standard implementation while maintaining structural similarity above 96%. The results demonstrate that the proposed simulation framework provides an accurate and efficient method for validating real-time image processing systems.Real-time systems, Sobel edge detection, HIL simulation, FPGA, Simulink, Image processing, Hardware modeling