SC-NeuroCore: A Universal Stochastic Substrate for Next-Generation Distributed Intelligence

SC-NeuroCore proposes a universal stochastic substrate for distributed intelligence based on probability-encoded bit-streams. Arithmetic reduces to simple logic (AND/MUX/FSM), enabling massively parallel compute within the stream and steep reductions in data movement. A Numba-accelerated, bit-sliced engine with hardware-style popcount realises vector operations at scale. Replacing pseudo-random with Sobol low-discrepancy sequences upgrades practical convergence, making short streams viable for both training-adjacent computation and inference. Demonstrated outcomes include multi-gigabit logical throughput and femtojoule-class energy per bit-operation (45-nm model assumptions), with robustness to injected bit-error rates. The architecture supplies a coherent software-to-hardware pathway: bit-true Python operators map to RTL for FPGA/ASIC without semantic drift. The manuscript summarises primitives (unipolar multiply via AND; scaled add via MUX; stream non-linearities via FSM), a stochastic LIF neuron, and stream-local STDP. Reproducibility notes cover stream generators (Sobol/Bernoulli), packed tensors and MAC traces. The aim is a thermoeconomic route to trillion-parameter-class cognition on edge-level power budgets.