Real-Time Erasure Conversion for Neutral Atom Processors via Systolic Drift Monitoring

Title Real-Time Erasure Conversion for Neutral Atom Processors via Systolic Drift Monitoring Description Real-time quantum error correction (QEC) in Neutral Atom (Rydberg) architectures faces unique challenges due to slow-evolving noise sources, such as atom loss, leakage, and intensity drifts in trapping lasers. Standard windowed decoders (e.g., MWPM or Union-Find) are fundamentally "blind" to these temporally correlated errors when the drift duration exceeds the decoder's memory window (L > W). This manuscript introduces the Systolic Drift Monitor (SDM), a hardware-efficient architectural primitive designed to overcome this topological blindness. Unlike standard decoders that optimize for correction within a finite window, the SDM optimizes for identifiability over an unbounded horizon. Implemented as a systolic array on FPGA, the SDM tracks the integrated syndrome flux of the system to detect non-Markovian drifts. Key Contributions: The Blindness Condition: A theoretical formalization of why finite-memory decoders cannot distinguish global temporal drifts from local boundary errors. Systolic Drift Monitor (SDM): A proposed hardware safety layer that operates with O(1) memory and deterministic latency (approx 1.4 microseconds). Erasure Conversion: Simulation results demonstrating that the SDM effectively converts correlated Pauli errors (which lower thresholds) into flagged Erasure errors (which have significantly higher thresholds). Neutral Atom Optimization: Analysis showing that the SDM's latency is negligible compared to the millisecond-scale cycle times of Neutral Atom processors, enabling it to function as a seamless "inter-cycle" safety check. Keywords Quantum Error Correction, Neutral Atoms, Rydberg Physics, FPGA, Real-Time Decoding, Erasure Conversion, Non-Markovian Noise, Systolic Arrays, Fault Tolerance. Notes This preprint presents the architectural specification and FPGA resource analysis for the SDM, targeting implementation on Xilinx UltraScale+ architectures.