Machine Learning-Based Congestion Optimization in VLSI Physical Design

The purpose of the current study is to implement the concept of Graph Neural Networks (GNNs) in decreasing the number of congestions when implementing VLSI circuit placement and routing. In VLSI, like other fields, congestion estimation fields on rules-of-thumb and heuristic approaches, which are challenging to use with larger designs. Rather, GNNs can work on the circuit layout to create a graph, in which the components form the nodes, and their connections are the edges, and this is far more spatial. Because the GNN model involves utilization of the ISPD benchmark data congestion, it can be considered that the model can predict which areas house the most critical hotspots of activity during optimization without negatively influencing the other design parameters. The results indicated that GNNs sang on a scalable basis and were performing better than heuristics about the solution of modern VLSI problems