Quantum Circuit Compilation for Superconducting Bus-Resonator Architectures

Superconducting quantum computers are fundamentally limited by restricted qubit connectivity. Bus-resonator architectures alleviate this constraint by enabling effective all-to-all interactions. This advantage, however, comes at the cost of significant operational overhead. Realizing the full potential of such hardware thus requires sophisticated compilation techniques that minimize this overhead. In this work, we present the first formalization of the underlying compilation problem for bus-resonator architectures amenable to so-called SAT-CP solvers. This formalization yields optimal solutions for small quantum circuits. For larger instances, we propose a linear-time heuristic. Experimental evaluations confirm that the formalization makes it possible to find optimal solutions even in vast search spaces and that the heuristic provides near-optimal compilation while scaling efficiently to circuits of practical size. Together, these contributions establish both a rigorous baseline and a practical path toward low-overhead compilation for superconducting bus-resonator devices.