Integrated ML and XAI Pipeline for Transistor Quantification in CMOS JK Flip-Flop Designs
Abstract
Customized database, created from the Cadence CMOS simulation setup, which is utilizedfor training the ML model.
Publication details
- Journal / source
- Zenodo (CERN European Organization for Nuclear Research)
- Publication date
- 13 January 2026
- Language
- EN
- Document type
- Dataset