PSK16 ε-Lattice Quantization Core — Deterministic Mapping, Weak-Symbol Analysis, and Multi-Format Reference Implementation (Defensive Prior Art)

# PSK16 ε-Lattice Quantization — Singular Core (Defensive Publication) **Version:** v3.3 (Frozen Core) **Author:** Mefail Baciqinovski (Derek Snyder) **License:** MIT **Status:** Public Defensive Publication / Prior Art Disclosure **Archive:** Zenodo (immutable record upon publication) --- ## 1. PURPOSE AND LEGAL INTENT (READ FIRST) This repository is **intentionally, explicitly, and irrevocably published as prior art**. The legal and technical purpose of this publication is to: - Publicly disclose the methods, algorithms, mappings, analyses, and implementations described herein;- Establish clear, timestamped **prior art** preventing future exclusive appropriation (including patent claims);- Enable open scientific review, replication, audit, and educational use;- Preserve these methods as permanently accessible, non-proprietary knowledge. No patent protection is claimed by the author for the disclosed material. Any later patent, proprietary, or exclusive claim over substantially similar techniques **must be evaluated in light of this disclosure**. Publication under the **MIT License** is deliberate and permanent. --- ## 2. SCOPE OF DISCLOSURE (WHAT IS BEING DISCLOSED) This work fully and unconditionally discloses: 1. A deterministic **ε-lattice phase quantization method** for PSK16 modulation;2. A parameterized lattice resolution **Z** (default Z = 60) independent of symbol order **M = 16**;3. A mathematically derived method for **weak symbol identification** based on geometric distance to lattice boundaries (not hard-coded);4. A complete, finite **lookup table (LUT)** mapping lattice steps to: - PSK symbol index, - Gray-coded symbol representation, - Weak-symbol flag, - Quantization error metrics;5. Explicit **quantization error bounds**, statistics, and histograms;6. **Phase ambiguity resolution** via nearest-lattice candidate ranking with confidence scoring;7. Optional **weak-symbol mitigation strategies** (parity metadata, neighbor averaging);8. Deterministic, multi-format exports: - JSON core specification, - CSV table, - Synthesizable Verilog ROM, - Verilog testbench, - Portable C header;9. Cryptographic **SHA-256 fingerprints** for all generated artifacts;10. Validation, benchmarking, and batch-processing utilities demonstrating generality. All algorithms are fully specified. No hidden heuristics, trade secrets, or undisclosed dependencies exist. --- ## 3. WHAT THIS WORK IS NOT This publication does **not**: - Claim novelty over basic PSK modulation, Gray coding, or quantization in isolation;- Restrict use, modification, redistribution, or commercial application;- Depend on proprietary hardware, firmware, or software;- Require network access, telemetry, or external services;- Assert performance guarantees beyond explicitly computed mathematical bounds. --- ## 4. TECHNICAL SUMMARY (PLAIN LANGUAGE) - The unit circle is divided into **Z equal angular steps** (the ε-lattice).- Each lattice step is mapped to the nearest PSK16 symbol center.- Because 360° does not divide evenly by 16, some symbols lie closer to lattice boundaries.- These are mathematically identified as **weak symbols**.- The mapping is precomputed into a table so hardware or software can: - Perform constant-time lookup, - Identify high-ambiguity cases, - Apply mitigation strategies if desired. The **maximum theoretical quantization error** is strictly bounded by: ε / 2 = (360° / Z) / 2 This bound is computed, enforced, and validated. --- ## 5. DETERMINISM AND REPRODUCIBILITY This artifact is: - Deterministic: identical inputs yield identical outputs;- Offline: no network access required;- Self-contained: Python standard library only;- Auditable: all outputs are cryptographically hashed;- Reproducible: regeneration steps are explicit and verifiable. A cryptographic fingerprint of the LUT content ensures bit-for-bit verification. --- ## 6. ARCHIVE CONTENTS Typical files included in this archive: - `psk16_core.json` Machine-readable core specification, LUT, analysis, and metadata. - `psk16_lut.v` Synthesizable Verilog ROM implementing the LUT. - `psk16_lut_tb.v` Verilog testbench for functional verification. - `psk16_lut.h` Portable C header for embedded or software implementations. - `psk16_lut.csv` Human-readable and spreadsheet-compatible LUT. - `manifest.json` SHA-256 hashes for every file in the archive. - `README.md` This document. --- ## 7. INTENDED USES (NON-EXHAUSTIVE) This disclosure supports, without limitation: - Digital communications education;- FPGA and ASIC design;- Software-defined radio (SDR);- Synchronization and phase recovery systems;- Safety-critical or auditable deterministic systems;- Accessibility-focused educational tooling. --- ## 8. DEFENSIVE PUBLICATION STATEMENT This work is published explicitly as a **defensive publication**. By placing this material in a permanent, timestamped public archive: - The author irrevocably dedicates the disclosed techniques to the public;- The disclosure bars future patent claims on substantially similar methods to the extent permitted by law;- The material may be freely used, studied, modified, redistributed, and cited. Any assertion of exclusive rights over the disclosed concepts should reference this publication and its cryptographic record. --- ## 9. LICENSE This work is licensed under the **MIT License**. --- ## 10. CITATION When citing this work, reference the associated Zenodo DOI and specify the version number. --- END OF DOCUMENT ## 11. ACCESSIBILITY + DISABILITY STATEMENT (UDL / INCLUSIVE DESIGN) This project is published with an explicit commitment to **disability access**, **Universal Design for Learning (UDL)** principles, and **equal access**. The intent is that disabled learners, disabled engineers, and assistive-technology users can study, verify, and reuse the work **without barriers**. ### Accessibility Commitments (Cut-and-Paste) - **Multiple means of representation (UDL):** The core concepts are provided in both human-readable documentation (README) and machine-readable formats (JSON/CSV), so users can access the material through the modality that works best for them (screen reader, braille display, magnification, plain text, structured data). - **Multiple means of action and expression (UDL):** The work supports different ways to engage and verify results: command-line generation, deterministic file outputs, cryptographic manifests, and cross-format exports (Verilog/C/JSON/CSV). Users may choose the workflow and tools compatible with their access needs. - **Multiple means of engagement (UDL):** The artifact is designed for incremental learning and auditing: small, reproducible steps, predictable outputs, and clear checkpoints (hashes and manifests) that reduce cognitive load and support confidence for learners. ### Technical Accessibility Features - **Offline by design:** No network requirement, no telemetry, no tracking. This supports users with limited connectivity, privacy needs, or assistive environments that restrict network access.- **Deterministic outputs:** The same inputs generate the same results, supporting learners who benefit from predictable behavior and repeatable verification.- **Plain-text friendly:** Documentation and outputs are readable in standard text tools and compatible with screen readers and refreshable braille displays.- **Structured data exports:** JSON and CSV enable accessible consumption via assistive workflows, spreadsheet tools, and custom accessibility pipelines.- **Auditability:** SHA-256 manifests enable independent verification, supporting trust and clarity for users who rely on step-by-step validation. ### Accessibility Scope and Limitations (Honest Disclosure) - This project **does not require** specialized UI, graphics, or proprietary tools to function. - Where diagrams or visualizations are added later, the project will aim to include **text equivalents**, **alt-text**, or **data-first representations** so the material remains accessible.- Hardware implementation accessibility depends on the user’s toolchain; however, the core is designed to remain usable through standard, widely supported text-based tooling. ### Equal-Access Intent The author’s intent is that this material be usable for education and professional engineering work by **disabled and non-disabled** users alike, including (non-exhaustively) users of: - Screen readers (VoiceOver, NVDA, JAWS)- Refreshable braille displays- Keyboard-only navigation- Magnification and high-contrast setups- Cognitive-access workflows that rely on predictable, structured outputs This statement is included to document inclusive intent and to encourage downstream users and derivative works to preserve and extend accessibility. ---