Density-Gradient Based Quantum Analysis of Nanowire Transistor

The semiconductor devices scaling are changing very rapidly, which has triggered a non-conventional physical effect called quantum confinement. This dominant effect must need to be considered for submicron transistor modeling. The conventional drift–diffusion (DD) models are not suitable and accurate for analyzing the carrier distribution, energy levels and spatial confinement. This paper concentrates on employing Density-Gradient (DG) based quantum model for analyzing 3-D nanowire transistors made out of silicon and germanium. COMSOL Multiphysics 6.3 [1] has been used as simulation software. Extensive Simulation results reveal increased threshold voltage due to quantum effect, higher electron density at the center, and strong electrostatic control for the gate-all-around (GAA) structure.