⬛ XCPUN FPGA crna kutija – dokaz životnosti (verifikacija na razini dizajna) - XCPUN FPGA Black-Box Alive Evidence Package (Design-Level Verification)

🔐 File checksums (XCPUN_Alive_Evidence_Package_v2.zip) Use these values in the “Related identifiers / Notes” or description section on Zenodo. MD59045a8a95356f49b7650255466d7bf58 SHA-107af73d2a70a27585187b13ebd9c0417f45927fe SHA-25667783768c00505411daeed91809a493456314f105b34504d898c1e2dc3c84b51 Dokazi se temelje na neintruzivnim mehanizmima koji se standardno koriste u sigurnosno-kritičnim i obrambenim hardverskim sustavima, uključujući: ugrađeni test (Built-In Test, BIT) na FPGA strani heartbeat (detekcija aktivnosti izlaznih signala) watchdog nadzor nad vremenskim odzivom integraciju crne kutije na vršnoj razini dizajna formalnu definiciju kriterija “ALIVE” (životnosti) Rezultati provedenih testova Primjenom navedenih mehanizama dobiveni su sljedeći rezultati na razini dizajna i integracije: potvrđeno je da se crna kutija može integrirati kao zatvoreni modul bez nerazriješenih ovisnosti potvrđeno je da su definirani ulazno-izlazni portovi konzistentni i implementabilni u FPGA okruženju potvrđeno je postojanje mjerljive aktivnosti na izlazima crne kutije, što omogućuje detekciju operativne prisutnosti putem heartbeat mehanizma potvrđeno je da watchdog mehanizam može pouzdano detektirati izostanak aktivnosti (zamrzavanje ili tiho otkazivanje) potvrđeno je da BIT logika može razlikovati normalno operativno stanje od greške bez uvida u internu implementaciju Na temelju navedenog utvrđeno je da dizajn posjeduje sposobnost dokazivanja životnosti (ALIVE) isključivo putem vanjski promatranog ponašanja, u skladu s pravilima crne kutije. Tumačenje pojma “ALIVE” U ovom kontekstu, pojam ALIVE znači da dizajn: reagira na takt i reset prema definiranim pravilima pokazuje promjenjivo i vremenski ograničeno ponašanje na izlazima omogućuje nadzor i detekciju zastoja bez pristupa internoj logici Pojam ne označava funkcionalnu ispravnost algoritama niti potvrdu fizičkog izvršavanja u siliciju. Važna napomena Ovaj paket ne tvrdi da je dizajn u trenutku objave bio izvršavan na fizičkom FPGA uređaju. Svi navodi odnose se isključivo na razinu dizajna i integracije, te pokazuju da je sustav: implementabilan u FPGA spreman za fizičku implementaciju sposoban dokazati operativnu prisutnost nakon učitavanja u hardver Interna implementacija crne kutije nije otkrivena. Verifikacija je provedena isključivo putem vanjski promatranog ponašanja, bez narušavanja IP-a. ---------------------------------------------- This collection contains an evidence package for an FPGA-targeted black-box system (XCPUn). The package documents design implementability and the capability to detect operational presence without exposing internal RTL logic, netlists, or protected intellectual property. The evidence is based on non-intrusive mechanisms commonly used in safety-critical and defence-grade hardware systems, including: FPGA-side Built-In Test (BIT) heartbeat monitoring (activity detection on observable outputs) watchdog supervision of temporal behaviour top-level black-box integration a formal definition of “ALIVE” (operational presence) criteria Results of the Performed Tests Applying the above mechanisms yielded the following results at the design and integration level: it was confirmed that the black-box core can be integrated as a closed module without unresolved dependencies it was confirmed that the defined input/output ports are consistent and implementable in an FPGA environment measurable activity on the black-box outputs was confirmed, enabling reliable detection of operational presence via heartbeat monitoring it was confirmed that the watchdog mechanism can reliably detect loss of activity, including frozen or silent-failure conditions it was confirmed that the BIT logic can distinguish normal operational presence from fault conditions without access to the internal implementation Based on these results, it was established that the design possesses the capability to prove operational presence (“ALIVE”) strictly through externally observable behaviour, in compliance with black-box constraints. Interpretation of the Term “ALIVE” In this context, the term ALIVE means that the design: responds to clock and reset according to defined rules exhibits time-bounded, observable changes on its outputs allows supervision and detection of stalled or non-responsive states without access to internal logic The term does not imply functional correctness of internal algorithms, nor does it imply execution on physical silicon. Important Note This package does not claim that the design was executed on physical FPGA hardware at the time of publication. All statements apply strictly to the design and integration level, demonstrating that the system is: implementable in an FPGA ready for physical deployment capable of proving operational presence once loaded onto hardware The internal implementation of the black-box core is not disclosed. Verification is performed exclusively through externally observable behaviour, without violating IP boundaries. 👤 Autori / Nositelj prava dr. Ladislav Gradečak • Xrealism ⚖️ Licenca Sva prava pridržana. © dr. Ladislav Gradečak – Xrealism Svaka redistribucija, izmjena ili komercijalna uporaba bez izričitog pisanog dopuštenja nije dopuštena.