⬛ XCPUn MiniSDK with FPGA Black-Box Core — Sanitized NOENV Release (Design-Level Evidence)

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Authors: Ladgrad Ladislav Gradečak
Cited by: 0

Abstract

🔐 File checksums (XCPUn_MiniSDK_with_BlackBox_FINAL_COMBINED_v4_NOENV.zip) MD594d060d33d2ec14f4f9bb0013b334dfb SHA-1bccf0c02f7f1c8fda2e41db2a582a81fd5c79011 SHA-256c3154084467f99ff201f533e8f94da2c7ecf99bf1c6dd582869810ac6ece6988 🧼 Sanitized release statement Sanitized release: This archive has been reviewed and sanitized. No environment files, credentials, secrets, API keys, tokens, or private configuration data are included. This collection contains a sanitized (NOENV) release of the XCPUn MiniSDK with an FPGA-targeted black-box core. The archive has been reviewed to ensure that no environment configuration files, credentials, secrets, API keys, or private data are included. The package documents design-level integration and implementability of an FPGA black-box system without exposing internal RTL logic, netlists, or protected intellectual property. The included materials demonstrate non-intrusive, defence-grade verification mechanisms commonly used in safety-critical hardware systems, including: FPGA-side Built-In Test (BIT) heartbeat-based activity detection watchdog supervision top-level black-box integration formal definition of “ALIVE” (operational presence) criteria Results and scope At the design and integration level, the package confirms that: the black-box core can be integrated as a closed module without unresolved dependencies the defined I/O interfaces are consistent and FPGA-implementable observable output activity enables detection of operational presence watchdog mechanisms can detect loss of activity or stalled states without internal visibility ⚠️ Important note: This release does not claim execution on physical FPGA hardware at the time of publication. All statements apply strictly to the design and integration level, demonstrating readiness for physical deployment and the capability to prove operational presence once loaded onto hardware. Internal implementation of the black-box core is not disclosed. Verification is performed exclusively through externally observable behaviour. -------------------------- Ova zbirka sadrži sanitirano izdanje (NOENV) XCPUn MiniSDK-a s FPGA-ciljanom crnom kutijom. Arhiva je pregledana kako bi se osiguralo da ne sadrži datoteke konfiguracije okoline, vjerodajnice, tajne, API ključeve niti privatne podatke. Paket dokumentira integraciju i implementabilnost na razini dizajna FPGA sustava crne kutije bez otkrivanja interne RTL logike, netlista ili zaštićenog intelektualnog vlasništva. Uključeni materijali demonstriraju neintruzivne, obrambeno-razinske mehanizme verifikacije koji se uobičajeno koriste u sigurnosno-kritičnim hardverskim sustavima, uključujući: ugrađeni test (Built-In Test, BIT) na FPGA strani detekciju aktivnosti temeljenu na heartbeat mehanizmu watchdog nadzor integraciju crne kutije na vršnoj razini dizajna formalnu definiciju kriterija “ALIVE” (operativne prisutnosti) Rezultati i opseg Na razini dizajna i integracije paket potvrđuje sljedeće: crna kutija može se integrirati kao zatvoreni modul bez nerazriješenih ovisnosti definirana ulazno-izlazna sučelja su konzistentna i implementabilna u FPGA okruženju promatrana aktivnost na izlazima omogućuje detekciju operativne prisutnosti watchdog mehanizmi mogu detektirati gubitak aktivnosti ili zaglavljena stanja bez uvida u internu logiku ⚠️ Važna napomena: Ovo izdanje ne tvrdi da je dizajn u trenutku objave bio izvršavan na fizičkom FPGA hardveru. Svi navodi odnose se isključivo na razinu dizajna i integracije, te pokazuju spremnost za fizičku implementaciju i sposobnost dokazivanja operativne prisutnosti nakon učitavanja u hardver. Interna implementacija crne kutije nije otkrivena. Verifikacija se provodi isključivo putem vanjski promatranog ponašanja. 👤 Creators / Rights Dr. Ladislav Gradečak • Xrealism ⚖️ License All rights reserved. © Dr. Ladislav Gradečak – Xrealism

Fields of Study & Subjects

Embedded Systems Design Techniques Physical Unclonable Functions (PUFs) and Hardware Security Embedded Systems and FPGA Applications

Publication details

Journal / source
Zenodo (CERN European Organization for Nuclear Research)
Publication date
27 January 2026