Catechon DSP Core v4.5 (Hardened Target) & Calibration Protocol

Zenodo (CERN European Organization for Nuclear Research) 2026 Open access

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Authors: Maksym Alekseevich Kovalevych
DOI: 10.5281/zenodo.18603214
Cited by: 0

Abstract

Internal engineering reference for Catechon v4.5 IP Core. Contains hardened Verilog source code and field calibration procedures for Xilinx Versal/RFSoC integration. Includes SIL-3 safety compliance updates. Proprietary IP (Catechon v4.5 Hardened). Available for academic and industrial partners upon request. NDA required for full access to source code and calibration protocols.

Fields of Study & Subjects

Embedded Systems Design Techniques Embedded Systems and FPGA Applications Physical Unclonable Functions (PUFs) and Hardware Security

Publication details

Journal / source
Zenodo (CERN European Organization for Nuclear Research)
Publication date
11 February 2026
Language
EN