Catalyst N1: A 131K-Neuron Open Neuromorphic Processor with Programmable Synaptic Plasticity and FPGA Validation

I present Catalyst N1, an open neuromorphic processor architecture comprising 128 cores, each containing 1,024 current-based leaky integrate-and-fire (CUBA LIF) neurons and 131K compressed sparse row (CSR) synapses. The design implements a fully programmable microcode learning engine with 16 registers and 15 opcodes, supporting spike-timing-dependent plasticity (STDP), three-factor eligibility-modulated reward learning, and homeostatic weight normalization. Each neuron features 24-bit state precision, dendritic compartment trees with configurable join operations, dual spike traces, stochastic threshold noise via per-neuron linear feedback shift registers, and per-synapse programmable delays up to 63 timesteps. Three synapse encoding formats: sparse, dense, and population-coded, reduce memory footprint for structured connectivity. A triple RV32IMF RISC-V embedded processor cluster provides on-chip supervisory control. Inter-core communication supports both barrier-synchronized mesh and asynchronous packet-routed network-on-chip (NoC) topologies. An accompanying software development kit offers a Python network builder, density-weighted compiler, cycle-accurate CPU simulator, GPU-accelerated simulator achieving 100–1000x speedup via PyTorch sparse CSR operations, and a hardware backend targeting Xilinx FPGAs. I validate a 16-core instance on an AWS F2 VU47P at 62.5 MHz neuromorphic clock (250 MHz PCIe interface) with dual-clock CDC. Across 25 RTL testbenches covering 98 test scenarios, Catalyst N1 achieves zero failures. On the Spiking Heidelberg Digits (SHD) spoken digit classification benchmark, a surrogate gradient-trained recurrent SNN deployed with 16-bit weight quantization achieves 85.9% test accuracy. Feature comparison demonstrates architectural feature parity with Intel's Loihi 1, with graded spike support extending into Loihi 2 territory.