Hybrid 2.5D/3D Integration of Photonic Chiplets and Compute Dies for Scalable Co-Packaged Optical Interconnects in AI Data Centers

Modern artificial intelligence and high-performance computing systems face critical bottlenecks in inter-chip communication as computational capabilities continue to advance beyond the limits of traditional copper-based interconnects and board-edge optical modules. Co-packaged optics emerges as a transformative solution by integrating photonic components directly within processor packages, dramatically reducing electrical path lengths and enabling unprecedented bandwidth densities while lowering energy consumption per transmitted bit. This article presents a comprehensive hybrid integration architecture that combines two-and-a-half-dimensional and three-dimensional packaging techniques to co-locate photonic chiplets with compute dies on silicon interposers. The article leverages micro-ring resonator-based wavelength division multiplexing on silicon photonic platforms to achieve high aggregate throughput while maintaining compatibility with advanced logic manufacturing processes. Through detailed co-design of packaging structures, electrical-optical interfaces, thermal management systems, and control algorithms, the architecture addresses key technical challenges that have historically impeded photonic integration efforts. Validation through multi-level simulations and physical prototypes demonstrates feasibility for rack-scale optical connectivity meeting the demanding requirements of distributed machine learning workloads. The article examines critical parameters that affect the timing of commercial adoption, such as manufacturing yield, serviceability, the need for standardization, and economic trade-offs. Results indicate that hybrid co-packaged optics architectures provide viable pathways for sustaining bandwidth scaling in next-generation data center fabrics serving artificial intelligence applications.