Convergence-Aware Processor

This paper introduces a novel architectural paradigm, Convergence-Aware Processing, and presents a Convergence-Aware Processor Architecture that integrates convergence monitoring and termination control directly into hardware. The processor executes iterative kernels until a programmable convergence criterion is satisfied, eliminating redundant iterations and reducing software overhead. We propose hardware extensions to the instruction set architecture (ISA) that enable programmers to express iterative computations naturally. The proposed architecture aims to improve performance, energy efficiency, and numerical robustness for a wide class of iterative workloads, offering potential speedups of 2–5× over conventional CPU implementations while reducing energy consumption by 30–50%.