A Hardware Accelerator Architecture for Fixed-Point Iterative Computation

This paper presents a novel hardware accelerator architecture for solving fixed-point problems of the form x = F(x). The proposed Fixed-Point Computation Accelerator (FPCA) implements a convergence-driven execution model that eliminates traditional software loop overhead by embedding iterative transformation, convergence detection, stagnation detection, and adaptive precision control directly in hardware. Unlike conventional processors, the FPCA treats computation as a process of state transformation until mathematical convergence criteria are satisfied. The architecture significantly accelerates numerical solvers, optimization algorithms, machine learning training, and scientific simulations. We describe the architecture, execution model, programmability aspects, and potential applications, along with a research plan for implementation and evaluation.