Scalable and Energy-Efficient Sparse Matrix-Vector Multiplication on Heterogeneous Architectures

Sparse matrix-vector multiplication (SpMV) is a fundamental computational kernel in numerous scientific and engineering applications. Its irregular memory access patterns and computational intensity pose significant challenges for achieving high performance on modern architectures. This paper presents a novel approach to SpMV on heterogeneous platforms, leveraging a combination of algorithmic optimizations and hardware-aware mapping strategies to maximize both performance and energy efficiency. We explore the use of specialized accelerator units alongside traditional CPUs and GPUs, dynamically partitioning the computation based on matrix sparsity structure and hardware capabilities. Experimental results demonstrate significant performance improvements and reduced energy consumption compared to existing SpMV implementations.