Implementation of Image Algorithms using Verilog HDL

The main theme of this paper is to construct on an FPGA platform a number of widely used digital image processing algorithms, including thresholding, inversion, contrast modification, brightness manipulation, and grey level translation. To prepare the input colour image for FPGA processing, it is first transformed to bitmap format and then, using MATLAB, to hexadecimal format. The algorithms are developed in Verilog HDL, and the simulation and synthesis platforms are Model Sim Altera and Intel Quartus Il. Therefore, five hex files are created, each of which represents the image that was processed using a certain algorithm. After that, MATLAB post-processes these outputs to recreate and display the finished pictures.