Phenomenological Simulation Model and Data for Frequency-Domain Device Fingerprinting via On-Chip Monitoring Sensors in FPGAs

Overview A reduced phenomenological model of the power supply and data acquisition chain present in the Digilent Basys 3™ FPGA development board was implemented in LTspice® to validate the theoretical predictions regarding aliasing phenomena and thermal drift of spectral peaks in on-chip sensor readouts. The model captures the fundamental subsystems involved in the variability chain: the upstream DC supply, the on-board switching voltage regulators, a temperature-sensitive clock reference, and the SAR ADC conversion stage. A parametric temperature sweep was conducted to verify that the spectral structure predicted by the aliasing and thermal drift equations is consistent with the simulated ADC output, prior to the experimental campaign on physical devices. Simulation Model Description Circuit Elements The LTspice schematic (Phenomenologic_Model.asc) comprises the following elements, which replicate the cascade of the power supply and acquisition chain of the Basys 3™ board: Element Description 5 V DC source Non-ideal supply with artificial harmonic components injected at 5, 10, 25, 100, and 500 kHz (100 mV amplitude each), emulating spurious content from external upstream subsystems. LT3633 (Dual-rail regulator) Switching voltage regulator providing the 1.0 V and 3.3 V output rails. Circuit configuration replicated from the official Digilent Basys 3 schematics. Behavioral model provided by Analog Devices within LTspice. LT3621 (Single-rail regulator) Switching voltage regulator providing the 1.8 V output rail. Circuit configuration replicated from the official Digilent Basys 3 schematics. Behavioral model provided by Analog Devices within LTspice. CMOS clock reference Emulation of the DSC1033 oscillator as a temperature-sensitive clock source. adapted to provide a 120 kHz reference clock signal for the ADCs. TCF: ±100 ppm/°C (deliberately set to approximately twice the nominal specification to improve visibility of thermal drift effects). Reference temperature: T₀ = 25 °C. Frequency variation follows: f(T) = f₀ × [1 + TCF × (T − T₀)]. 3× AD4056 (12-bit SAR ADC) Three low-power SAR ADCs configured to sample each regulator output rail. Nominal sampling rate: Fs₀ = 120 kHz, simulating a prescaled clock signal derived from the temperature-sensitive oscillator. Selected as a faithful approximation to the undisclosed ADC architecture inside the Xilinx XADC. Solver Configuration Due to the mixed nature of the behavioral models (switching regulators and SAR ADCs), the following solver options were required to ensure convergence: .options method=gear reltol=0.01 trtol=5 These settings remain within the tolerance ranges recommended by Analog Devices for behavioral simulations of switching regulators. Data Description Temperature Sweep Parameters Parameter Value Temperature range 10 °C to 40 °C Temperature step 2.5 °C Number of temperature points 13 Samples per channel per temperature 4000 Monitored channels 3 (1.0 V, 1.8 V, 3.3 V) File Naming Convention Each CSV file follows the pattern TX.csv, where X represents the temperature at which the data were acquired. A p character is used as a decimal separator where applicable. CSV Column Description Each CSV file contains 4000 rows (one per ADC conversion) and the following columns: Column Description index Zero-based sample index (0 to 3999). time Simulation time (in seconds) at which the conversion was triggered. V(vorti1v0) Voltage value (in volts) sampled by the ADC monitoring the 1.0 V rail, captured at the rising edge of the ADC clock signal. V(vorti1v8) Voltage value (in volts) sampled by the ADC monitoring the 1.8 V rail, captured at the rising edge of the ADC clock signal. V(vorti3v3) Voltage value (in volts) sampled by the ADC monitoring the 3.3 V rail (Span was down-scaled to 1.8V via voltage divider), captured at the rising edge of the ADC clock signal.