Artifact of the paper: Backend Code Generation for Graph DSLs Targeting Diverse Accelerator Platforms

Sparse graphs are ubiquitous in real and virtual worlds. With the phenomenal growth in semi-structured and unstructured data, the sizes of the underlying graphs have witnessed rapid growth over the years. Analyzing such large structures necessitates parallel processing, which is challenged by the intrinsic irregularity of sparse computation, memory access, and communication. It would be ideal if programmers and domain experts could focus only on the sequential computation while a compiler automatically generates the parallel code. At the same time, the diversity of target hardware devices means that achieving optimal performance often requires programming in device-specific languages or frameworks.Our goal in this work is to focus on a graph DSL that allows domain experts to write almost-sequential code and generate parallel implementations for different accelerators from the same algorithmic specification. In particular, we illustrate code generation from the StarPlat graph DSL for NVIDIA, AMD, and Intel GPUs using CUDA, OpenCL, SYCL, HIP, and OpenACC programming languages. Using a suite of ten large representative graphs and four popular algorithms, we present the efficacy of StarPlat’s versatile code generator.