Computer Architecture as a Security Discipline: From Branch Predictors to Accelerators

Volume 2 of 10 in the Engineering-to-Research Monograph Series. Most security engineers reason about software and treat the processor beneath it as a trusted black box, but the optimizations that define modern performance, namely branch prediction, speculation, caching, and specialization, are also the mechanisms through which information leaks. This report argues that computer architecture is a security discipline. It builds the case from the author's hands-on architecture work, a Verilog tournament branch predictor and a quantitative comparison of a tensor processing unit against a GPU and a general-purpose CPU, and connects each topic to its security implication: branch-prediction-unit side channels, cache timing channels as the disclosure primitive, and the isolation problems of shared, heterogeneous accelerators. The unifying claim is a coupling thesis: at the microarchitecture, performance and security are a single quantitative trade-off. The report distills the argument into two design principles (Optimization Is Attack Surface; Security as a Quantitative Trade-Off) and a bounded competency model.The paper and figures are licensed CC BY 4.0; companion code is released under the MIT License. This work contains no confidential or proprietary employer information.