Research Progress on CMOS Leakage Current Optimization and Low-Power Design

With the continuous scaling of semiconductor technology into the nanometer regime, leakage current in CMOS integrated circuits has become a major bottleneck limiting low-power design and performance improvement. This paper focuses on the leakage current optimization, systematically analyzing representative low-power techniques from both device and circuit perspectives. At the device level, a combined low-temperature annealing and oxidation process is employed to effectively suppress carbon vacancy defects, thereby reducing the reverse leakage current in 4H-SiC diodes. At the circuit level, the Input Vector Analysis and Transistor Stacking (IVATS) technique minimizes standby current through the stacking effect, while the feedback structure low-power adder improves computational delay along with leakage reduction. The results show that all three approaches achieve significant leakage suppression; however, they still face limitations in terms of applicability, design complexity, and process scalability. To address these issues, this work provides a critical assessment and proposes corresponding improvement directions, including process parameter optimization, enhanced design automation, and cross-layer co-optimization. It is concluded that the integration of device-level process improvements with circuit-level architectural optimization is a key pathway toward achieving high performance and low power consumption in advanced CMOS technology nodes.