A review of In-Memory Computing with Non-Volatile Memory: challenges and opportunities

Traditional von Neumann architectures suffer from severe energy and latency overheads due to intensive data movement between memory and processing units. In-Memory Computing (IMC) integrates computation within memory arrays, greatly mitigating this bottleneck. This paper provides a comprehensive review of IMC principles, implementations, and challenges across SRAM, DRAM, and non-volatile memories (NVMs) such as RRAM, MRAM, and PCM. We summarize architectural advances, device-level constraints, and system-level opportunities, with emphasis on the emerging class of resistive NVM-based IMC accelerators. Furthermore, we highlight engineering trade-offs, real-world application scenarios, and current industrial standardization efforts, offering guidance toward large-scale deployment of IMC technologies.