Design and Verification of SRAM Using GPDK using 45nm Technology
Abstract
Highlights: · Presents a complete design and verification methodology for SRAM cells using GPDK 45 nm technology in Cadence Virtuoso. · Explains the transistor-level operation of the SRAM cell, verifying MOSFET functionality during read, write, and hold modes. · Performs schematic design, layout implementation, and post-layout verification including DRC and LVS checks. · Analyzes key performance parameters such as static noise margin (SNM), power consumption, access delay, and leakage current. · Validates the correctness and reliability of the SRAM design through pre-layout and post-layout simulations under 45 nm process constraints.
Fields of Study & Subjects
Low-power high-performance VLSI design
Physical Unclonable Functions (PUFs) and Hardware Security
Radiation Effects in Electronics
Publication details
- Journal / source
- INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
- Volume
- 10
- Issue
- 01
- Pages
- 1–9
- Publication date
- 3 January 2026