Design and Implementation of SRAM and SDRAM Using Cadence Virtuoso

Abstract This paper presents the design and implementation of a 64-bit SRAM and SDRAM memory architecture using Cadence Virtuoso .The main objective is to understand how static and dynamic memories are built at the transistor level and to analyze their performance .The SRAM is designed using a 6T cell ,while the SDRAM includes basic blocks such as decoders ,control logic, and refresh circuitry .All circuits are created and tested through schematic design and simulation. Important parameters like access time, power consumption, proper read/write operation are observed. The results show the both memory designs work correctly and meet the basic requirements for small VLSI applications. Keywords: SRAM, SDRAM, Cadance, Read- Write operation.