Secure Data Transmission Using Verilog HDL Based AES Architecture

The Advanced Encryption Standard (AES) is one of the most widely used symmetric encryption algorithms for securing digital communication and data storage. However, its high computational complexity and power consumption present significant challenges for resource-constrained hardware environments such as embedded systems and Internet of Things (IoT) devices. This paper presents the design and implementation of a low-power AES-128 encryption and decryption architecture using Verilog HDL on FPGA. The proposed design employs optimized S-Box substitution, pipelined round transformations, and flip-flop–based clock gating to minimize dynamic power dissipation without compromising encryption throughput or security strength. The complete AES core, including encryption, decryption, and key expansion, is implemented and functionally verified through simulation. Synthesis and power analysis are carried out using Xilinx design tools, and the design is validated on an Artix-7 FPGA. Experimental results demonstrate a significant reduction in power consumption with only a marginal increase in area and negligible impact on timing performance when compared to conventional AES implementations. The proposed architecture therefore provides a scalable and energy-efficient solution suitable for low-power cryptographic applications in modern embedded and IoT systems.