The design and verification of a SFIFO module using system verilog based UVM

The increasing complexity of Integrated Circuits (ICs) and System-on-Chip (SoC) designs necessitates robust and scalable verification methodologies to ensure functionality, reduce bugs, and shorten time-to-market. Traditional directed test benches are no longer sufficient to meet these verification demands. This paper presents the design of a Synchronous First- In-First-Out (SFIFO) buffer using Verilog HDL and its functional verification using System Verilog and Universal Verification Methodology (UVM). The FIFO is designed with a dual-port RAM structure, enabling concurrent read and write operations in a single clock domain. A comprehensive UVM testbench has been developed that includes sequencers, drivers, monitors, scoreboards, and a reference model. The simulation and verification were performed using Xilinx Vivado and QuestaSim.