The Maha_Astra Framework: A Unified Physics-Informed EDA and Device Architecture for Sub-2nm VLSI Pathfinding

The Maha_Astra Framework represents a unified mathematical engine linking thermal, timing, and power signatures. By synthesizing the scientific legacies of Ramanujan, Bose, Saha, and Bhabha, this work introduces a synthesizable SystemVerilog monitor capable of real-time on-chip self-correction and reliability-aware sign-off for post-CMOS nodes.