Analytical Modeling and Sub-60 mV/dec Switching Performance of 2nm WSe2 FETs via Bose-Saha-Ramanujan Kinetics

This paper introduces the SBR Transistor, a steep-slope logic device designed to bypass the 60 mV/dec Boltzmann limit. By utilizing Saha-ionization and Bose-Einstein excitonic condensation in WSe2 channels, we propose a switching mechanism grounded in quantum statistical mechanics. We further utilize Ramanujan’s Mock Theta functions to engineer non-linear tunneling barriers, suppressing off-state leakage at the 1nm node.