Dielectric integration and interface defect engineering in β-Ga2O3 metal-oxide-semiconductor (MOS) devices

High-quality dielectrics are crucial for metal-oxide-semiconductor (MOS) device performance, demanding low leakage current, high breakdown strength, and superior interfaces. This necessitates minimal defect density and sufficient energy barriers at both sides/interfaces of the dielectric to prevent carrier injection into the dielectric. This paper explores the challenges of integrating dielectrics in β-Ga2O3 MOS devices. The thermal stability of dielectrics is of particular importance because they are subjected to a range of thermal treatments in the manufacturing process. Key integration aspects, including surface treatments, roughness, deposition techniques, dielectric choices, and annealing processes, are discussed using new and existing data collected across a broad range of dielectrics. The focus is on minimizing pre-existing interface defects, including border traps, that contribute to performance instabilities like hysteresis, threshold voltage shifts, and mobility degradation. By addressing these challenges, improved dielectric integration can lead to enhanced β-Ga2O3 MOS device reliability and performance.